Integrated circuits typically include a number of input/output terminals used for communication with external circuitry. Recently developed communication networks can now transmit signals between circuitry at a rate faster than the capacity of many integrated circuits. As data is transmitted at increasingly higher speeds, new circuitry and methods are needed to accurately transmit data between integrated circuits having varying transmission rates. For example, an integrated memory device such as a dynamic random access memory (DRAM) includes both control terminals for receiving memory control signals, and data terminals for bi-directional data communication with an external system or processor. As data are transmitted at higher speeds between the DRAM external terminals, a better design of input/output drivers is needed to maintain desired electrical signaling levels. The output pins of the DRAM are conventionally connected to other circuit components by transmission lines. Ideally, input/output drivers should be designed to improve control of the input/output resistance to prevent impedance mismatch in the transmission lines.
Conventionally, circuits are integrated into an output driver of a memory system to improve communication speeds and reliability. Variations in process, voltage, temperature and other factors may cause the output drivers to overshoot or undershoot desired signal levels. Consequently, the impedance mismatch of the output driver results in reduced timing and voltage margins that impact signal integrity. Therefore, calibration circuits are designed with adjustment transistors for applying adjustment signals to the output driver to properly match the output impedance. Data is transferred more successfully and reflection is minimized when the output driver is designed to better match the required output impedance.
A conventional digital calibration circuit 100 used by an output driver in DRAM is shown in FIG. 1. A PMOS transistor 105 having a source coupled to a voltage supply includes a drain coupled to the sources of a plurality of PMOS transistors 110 and a resistor 115 in parallel. The drains of the PMOS transistors 110 are coupled to an external resistor 125, which forms a voltage divider whose output is at node 120. The voltage divider replicates a pull-up circuit of the output driver in series with a constant external impedance represented by the resistor 125. During calibration, the PMOS transistors 110 provide adjustments to the output voltage ZQ, which will be further described later. The output voltage ZQ of the voltage divider at node 120 and a reference voltage signal VREF are connected to the inputs of a differential comparator 130. The outputs of the differential comparator 130 are then connected to a filter 135. The output of the filter 135 is in turn coupled to a binary search circuit 140 that generates adjustment signals PADJ<0:m> based on the filtered signals from the filter 135. The adjustment signals PADJ<0:m> are then returned to the adjustment transistors 110 in a feedback loop to update or adjust the output voltage ZQ until it is approximately equal to VREF. The adjustment transistors 110, the filter 135 and the binary search circuit 140 will now be described in detail.
As explained, the voltage divider configuration of the calibration circuit 100 is designed to replicate a pull-up circuit of the output driver to determine the proper adjustment for matching the pull-up output impedance. In operation, the gate of the PMOS transistor 105 is coupled to ground to keep the PMOS transistor 105 constantly turned ON in order to mimic the pull-up circuit of the output driver when in operation to calculate the adjustment signal for calibrating the pull-up output impedance. The PMOS transistor 105, when turned ON, couples the adjustment transistors 110 and resistor 115 to the voltage supply VCC. Each adjustment transistor 110 is designed to have twice the width of the preceding transistor of the parallel configuration. The parallel configuration of the adjustment transistors 110 has a total transistor width, and hence a conductance, of 2m*WP, where m+1 represents the total number of transistors and WP represents the width of the first transistor. Each adjustment transistor 110 provides an adjustment step to the output voltage ZQ when selected.
The adjustment transistors are selected when the gate of the transistor 110 receives a LOW PADJ<0:m> signal assignment for that particular transistor 110 from the adjustment signal PADJ<0:m> provided by the binary searcher 135. Adjustment transistors 110 are selected according to the adjustment signal PADJ<0:m> in a feedback configuration from the binary searcher 140 after a comparison is made between the output voltage ZQ to the reference voltage signal VREF, and an adjustment is calculated. The reference voltage signal VREF is typically set to VCC/2. The comparator 130 generates two output signals, VA and VB, having three possible states as a result of the comparison. When the input voltages ZQ and VREF are comparable and cannot be distinguished, the comparator 130 makes VA and VB both either high or low, depending on the design of the comparator 130. If the output voltage ZQ is less than VREF, then the comparator 130 makes VA high and VB low. If the output voltage ZQ is greater than VREF, then the comparator 130 makes VA low and VB high. Due to noise and other limitations of the comparator 130, the output signals VA and VB may not stabilize to a particular state within the allotted time by the comparator, although statistically they represent a particular state.
The signals VA and VB are sent to the filter 135 so that the particular states of the output signals VA and VB may be sufficiently resolved. As a consequence of noise and the finite response time of the comparator 130, VA and VB may not settle on a particular state although statistically they represent a particular state. The filter 135 is designed to determine the correct state represented by VA and VB. The filter 135 has predetermined threshold values and a pre-defined time to reach the threshold values, and provides a signal to the binary searcher 140 indicating whether VA is greater than or less than VB based on which predetermined threshold value is reached first. If neither of the threshold values are reached after the pre-defined time, the filter 135 signals to the binary searcher 140 that VA equals VB.
The binary searcher 140 makes a decision to either stop the calibration or adjust the adjustment signals PADJ<m:0> based on the resulting signal from the filter 135. As further calibration of the adjustment signal PADJ<m:0> is needed, the binary searcher 140 generates a control signal to iteratively adjusts the signals PADJ<m:0> by a particular step size that depends on the selected combination of adjustment transistors 110. Initially, the binary searcher 140 begins the calibration by instructing the last adjustment transistor to turn ON, generating a signal PADJ<m> whose width is approximately half of the total width of adjustment transistors, ½(2m*WP). From this midpoint, the binary searcher 140 may provide further instructions to adjust upward or downward in iterative steps to calibrate the voltage output ZQ as close as possible to the reference VREF. With each iteration, the step size is reduced by half the width of the previous step. For example, if the first iteration turns ON adjustment transistors 110 having a width 2m*WP, then the second iteration will turn ON adjustment transistors 110 having a width of ½(2m*WP), the third iteration will turn ON transistors having a width of ¼(2m*WP), and so forth. Since there are a total of m+1 transistors 110, each set of adjustments are limited by a total of m steps, with the end objective being to match the output voltage ZQ as closely as possible to the reference voltage VREF. The binary searcher 140 adjusts the adjustment signal PADJ<m:0> such that when it stops, the ZQ voltage equals or approximates VREF, and accordingly, the resistance of the replicated pull-up circuit of the driver equals or approximates the external resistance of resister 125. If after m steps, the adjustment signal PADJ<m:0> requires further calibration, the binary searcher 140 repeats the iterative steps, starting once again from the midpoint until the ZQ voltage is closely matched to VREF or the searcher finishes in steps. The final adjustment signal PADJ<m:0> is then provided to the output driver for properly adjusting the output impedance.
Although the calibration circuit 100 sufficiently matches the output impedance of the output driver to the impedance of the resistor 125, the filtering time of the filter 135 may be unnecessarily long for evaluating ZQ and VREF signals. In the case of when the difference in magnitude between the voltage ZQ and the voltage VREF is large, the threshold values are likely determinable irrespective of noise and other minor interferences, therefore the signals may be assessed without significant filtering. One problem with the conventional calibration circuit 100 is the filter 135 and the binary search 140 do not discriminate between when the difference in magnitude of the ZQ and VREF voltages are large or small. In the conventional calibration circuit 100, the filter 135 is induced to unnecessarily filter signals whose states are determinable, and therefore prolonging the calibration time.
Another problem associated with the conventional calibration circuit 100 is that excessive over-compensation may occur as the binary searcher 140 iteratively adjusts the adjustment signal PADJ<m:0> by a particular step size that may be larger than the difference in magnitude of ZQ and VREF. Additionally, the binary searcher 140 may be forced to excessively repeat the iterative process until a sufficient adjustment is determined due to over-compensation, which results in further delays. For ZQ and VREF voltages whose magnitudes are closer together, it is not necessary to make adjustments with large step sizes that only results in over-compensation. Typically over-compensated adjustments require recalibration and re-adjustments, and unnecessarily prolongs the overall calibration time of the system.
Although the problems and limitations described above have been explained in the context of the pull-up circuitry of a driver, it should be understood that calibration circuits for calibrating the output impedance of pull-down circuitry using NMOS transistors are also subject to the same limitations and problems. There is therefore a need for a more efficient calibration circuit capable of more quickly detecting the difference in magnitude between the output voltage ZQ and the reference voltage VREF to adjust the step size accordingly, thereby reducing the overall calibration time.